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? e966381a1x-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. description the CXB1572Q achieves the 2r optical-fiber communication receiver functions (reshaping and regenerating) on a single chip. this ic is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. features auto-offset canceler circuit signal interruption alarm output 2-level switching function of identification maximum voltage amplitude for alarm block single 3.3 v power supply applications fddi : 125 mb/s sonet/sdh : 155.52 mb/s escon : 200 mb/s fiber channel : 265.625 mb/s atm : 155.52 mb/s absolute maximum ratings supply voltage v cc ?v ee ?.3 to +7.0 v storage temperature tstg ?5 to +150 ? input voltage difference : i v d ?v d i vdif 0 to +2.5 v sw input voltage vi v ee to v cc v output current (continuous) i o 0 to 50 ma (surge current) 0 to 100 ma recommended operating conditions supply voltage v cc ?v ee 3.0 to 3.6 v termination voltage (for data/alarm) v cc ?v t1 1.8 to 2.2 v termination voltage (for alarm 2) v t2 v ee v termination resistance (for data/alarm) r t1 46 to 56 ? termination resistance (for alarm 2) r t2 460 to 560 ? operating temperature ta ?0 to +85 ? structure bipolar silicon monolithic ic post amplifier for optical fiber communication receiver 32 pin qfp (plastic) CXB1572Q
? CXB1572Q block diagram and pin configuration q v cc da sd q sd v cc d v cc da v cc a up down cap2 cap3 nc nc nc v cc a v cc d v ee a v ee d nc cap1 r2k r3k peak hold limiting amplifier block peak hold alarm block 29 26 32 30 31 28 27 20 25 23 22 21 18 19 8 2 1 6 7 5 16 14 12 11 10 9 13 15 r1 r2 r1 r2 4 3 ? v r3 r4 24 cap1 v cc p v ee i sw v cc a d d v cc a rp 17 nc
3 CXB1572Q pin description 60k 40k v ref v ee a v cc a 4 31 30 vcca v ee a sw 986 123.4 123.4 vcs 3 2 1 5 32 v cc a v ee a 100 100 1.5k 1.5k 10k 10k 100p 200 200 3k 2k 5 6 11 10 9 8 typical pin pin no. symbol voltage (v) equivalent circuit description dc ac 1 2 3 4 5 6 7 8 9 10 11 v cc p v cc a v ee i sw d d v cc a cap1 r2k r3k cap1 0 v 3.3 v 0 v (open) or 3.3 v 1.3 v 1.3 v 0 v 1.8 v 1.8 v 0.9 v to 1.7 v 0.9 v to 1.7 v positive power supply for external power supply. generates the default voltage between up and down. the voltage (5.3 mv for input conversion) can be generated between up and down (pins 30 and 31) as alarm setting level 1 by this pin to open. the voltage (12 mv for input conversion) can be generated as alarm setting level 2 by connecting this pin to v ee a. switches the identification maximum voltage amplitude. high voltage when open; the identification maximum voltage amplitude becomes 50 mvp-p. low voltage when connecting this pin to v ee ; the amplitude becomes 20 mvp-p. limiting amplifier block input. be sure to make this input with ac coupled. positive power supply for analog block. pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 2 k ? is connected between pins 8 and 9; 3 k ? between pins 10 and 11. a resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and dc feedback gain can be varied due to compensate the input duty cycle distortion.
4 CXB1572Q v ee d v cc da 21 22 v ee d v cc da 19 18 typical pin pin no. symbol voltage (v) equivalent circuit description dc ac 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v ee a v cc a v ee d v cc d nc q q v cc da sd sd v cc da v cc d nc 3.3 v 0 v 3.3 v 0 v 0 v 0 v 0 v 0.9 v to 1.7 v 0.9 v to 1.7 v 0.9 v to 1.7 v 0.9 v to 1.7 v negative power supply for analog block. positive power supply for analog block. negative power supply for digital block. positive power supply for digital block. no connected. data signal output. terminate this pin in 50 ? at v tt = 2 v. positive power supply for output buffer. alarm signal output. terminate this pin in 50 ? at v tt = 2 v. positive power supply for digital block. positive power supply for digital block. no connected.
5 CXB1572Q 10p 10p v cc a v ee a 80 5a 5a 80 29 28 200 200 31 30 vcca v ee a sw 986 123.4 123.4 vcs 3 typical pin pin no. symbol voltage (v) equivalent circuit description dc ac 28 29 30 31 32 cap3 cap2 down up v cc a 1.8 v 1.8 v 1090 mv (for v ee i = 3.3 v) 1020 mv (for v ee i = 3.3 v) 0 v connects a peak hold circuit capacitor for alarm block. 470 pf should be connected to v cc a each. cap2 pin peak hold capacitor connection for alarm level setting block. cap3 pin peak hold capacitor connection for limiting amplifier signal. connects a resistor for alarm level setting. default voltage can be generated without an external resistor. (please refer to pin description of pin no. 3.) positive power supply for analog block.
6 CXB1572Q power supply q/q sd/sd high output voltage q/q sd/sd low output voltage sd/sd high output voltage 2 sd/sd low output voltage 2 sw high input voltage sw low input voltage sw high input current sw low input current d/d input resistance internal resistance 1 for alarm level setting internal resistance 2 for alarm level setting resistance between v cc a and v cc p pare ratio of internal resistance 2 for alarm level setting resistance between cap1 and r2k resistance between cap1 and r3k electrical characteristics dc characteristics (v cc = gnd, v ee = 3.0 v to 3.6 v, ta = 40 to +85 c, v cc = v cc d, v cc da, v cc a v ee = v ee d, v ee a) item i ee v oh v ol v ohb v olb v ih v il i ih i il rin ra1 ra2a, b rp ra2 r3 r4 r t1 = 51 ? , v t1 = v cc 2 v termination, ta=0 to 85 c r t2 = 510 ? , v t2 =v ee termination, ta=0 to 85 c refer to fig. 3. refer to fig. 3. ra2a/ra2b 56 1025 1810 1025 1860 500 v ee 60 1109 739 93 3.3 0.97 1470 2210 40 1479 986 123 5 1970 2960 29 830 1550 700 1500 0 v ee +500 2 1849 1233 154 6.9 1.03 2470 3700 ma mv a ? ? symbol min. typ. max. unit conditions
7 CXB1572Q maximum input voltage amplitude amplifier gain (except for output buffer) identification maximum voltage amplitude of alarm level hysteresis width sd response assert time sd response deassert time sd response assert time for alarm level default sd response deassert time for alarm level default alarm setting level 1 for default alarm setting level 2 for default propagation delay time q/q sd/sd rise time q/q sd/sd fall time ac characteristics (v cc = gnd, v ee = 3.0 v to 3.6 v, ta = 40 to +85 c, v cc = v cc d, v cc da, v cc a v ee = v ee d, v ee a) item vmax gl vmina1 vmina2 ? p tas tdas tasd tdasd vdef1 vdef2 t pd tr tf 1600 52 20 50 3 0 2.3 0 2.3 4.3 10.5 1.2 0.45 0.45 6 5.3 12.0 1.7 0.85 0.85 7 100 100 100 100 6.3 13.5 2.6 1.3 1.3 mvpp db mvpp db s mv ns symbol min. typ. max. unit conditions ? 1 v up v down = 100 mv, vin = 100 mvpp (single ended), sw pin: high peak hold capacitance of 470 pf; connect v ee i to v ee . ? 2 v up v down = 100 mv, vin = 1 vpp (single ended), sw pin: high peak hold capacitance of 470 pf; connect v ee i to v ee . ? 3 vin = 50 mvpp (single ended), sw pin: low peak hold capacitance of 470 pf; connect v ee i to v ee . ? 4 vin = 1 vpp (single ended), sw pin: low peak hold capacitance of 470 pf; connect v ee i to v ee . single-ended input sw pin: low, single-ended input sw pin: open high, single-ended input alarm level is default value low high ? 1 high low ? 2 low high ? 3 high low ? 4 up,down,v ee i pins ;open, connect sw pin to v ee up,down,sw pins ;open, connect v ee i to v ee d to q r t1 = 50 ? , v t1 = v cc 2 v termination , v ee = 3.3 v, ta=0 to 85 c 20 % to 80 %
8 CXB1572Q dc electrical characteristics measurement circuit v v v v 51 51 51 51 c3 c3 v v v v v vs vd c1 c1 a v ee 5v v c2 v 2v v t1 v a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4 rp
9 CXB1572Q ac electrical characteristics measurement circuit z0=50 z0=50 z0=50 z0=50 oscilloscope 50 ? input 0.22f 0.022f 0.022f v ee v cc +3v +2v v r ex1 r ex2 470pf 470pf 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold ? v peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4 rp
10 CXB1572Q application circuit c2 0.22f c1 0.022f v ee 5v c1 0.022f 51 51 51 51 v t1 2v 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 peak hold peak hold alarm block limiting amplifier block r1 r1 r2 r2 r3 r4 rp v ? c3 330pf application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXB1572Q c1 c1 c2 r1 r1 r2 r2 to ic interior d r3 r4 5 6 8 9 10 11 fig. 1 f1 f2 frequency gain feedback frequency response amplifier frequency response fig. 2 notes on operation 1. limiting amplifier block the limiting amplifier block is equipped with the auto-offset canceler circuit. when external capacitors c1 and c2 are connected as shown in fig. 1, the dc bias is set automatically in this block. external capacitor c1 and ic internal resistor r1 determine the low input cut-off frequency f2 as shown in fig. 2. similarly, external capacitor c2 and ic internal resistor r2 determine the high cut-off frequency f1 for dc bias feedback. since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the c1 and c2 so as to avoid the occurrence of peaking characteristics. the target values of r1 and r2 and the typical values of c1 and c2 are as indicated below. when a single-ended input is used, provide ac grounding by connecting pin 6 to a capacitor which has the same capacitance as capacitor c1. r1 (internal): 1.5 k ? r2 (internal): 10 k ? f2: 4.8 khz f1: 72 hz c1 (external): 0.022 f c2 (external): 0.22 f 2 k ? is incorporated between pins 8 and 9; 3 k ? between pins 10 and 11. a resistance value which is to be inserted in parallel with a capacitor c2 can be selected 5 ways ( , 5 k ? , 3 k ? , 2 k ? , 2 k//3 k ? ) by external wiring, and dc feedback can be varied.
12 CXB1572Q 2. alarm block in order to operate the alarm block, give the voltage difference between pins 30 and 31 to set an alarm level and connect the peak hold capacitor c3 shown in fig. 3. this ic has two setting methods of alarm level; one is to leave pins 30 and 31 open to set an alarm level default value (5.3 mv or 12 mv for input conversion). default value of alarm level is 5.3 mv for input conversion by leaving pin3 to open,12 mv by connecting pin3 to v ee. the other is to connect pin 3 to v ee and set a desired alarm level using the external resistors r ex1 and r ex2 and r ex3 shown in fig. 3. connect r ex1 between pins 30 and 31, or connect r ex3 between pin 30 and v cc when less alarm level is desired to be set than its default value; connect r ex2 between pin 31 and v cc potential when more alarm level is desired to be set than its default value. however, the pin 31 voltage must be higher than that of pin 30. refer to figs. 7 to 9 for this alarm level setting. this ic also features two-level setting of identification maximum voltage amplitude for the alarm function. the amplitude is set to 50 mvp-p when pin 4 is left open (high level) and it is set to 20 mvp-p when pin 4 is low level. therefore, noise margin can be increased by setting pin 4 to low level when small signal is input. the relation of input voltage and peak hold output voltage is shown in fig. 5. in the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6 db) as shown in fig. 4. the c3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. the electrical characteristics for the sd response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of fig. 6. the typical values of r ex1 , r ex2 , r ex3 and c3 are as follows: (approximately 10 pf capacitor is built in pins 28 and 29 each.) r ex1 : 400 ? (when the alarm level is set to 3 mv for input conversion.pin3; open,connect pin4 to v ee ) r ex2 : 4k ? (when the alarm level is set to 15 mv for input conversion.connect pin3 to v ee, pin4; open) r ex3 : 6.2 k ? (when the alarm level is set to 3 mv for input conversion.pin3; open,connect pin4 to v ee ) c3 : 470 pf the table below shows the alarm logic. from limiting amplifier peak hold sd sd vcca 10p vcca 10p vcc c3 vcc peak hold ra1, ra2a and ra2b values are typical values c3 ? v 31 30 29 28 vcc r ex1 r ex2 4 3 vcc r ex3 ra2b 123.4 ra1 v cc a internal ic external ic 30 31 ra2a 123.4 986 vcs 3 v ee a optical signal input state signal input signal interruption high level low level low level high level sd sd fig. 3
3db 3db alarm setting input level hysteresis input electrical signal amplitude sd output high level low level small large v das v as v das deassert level v as assert level 13 CXB1572Q fig. 4 fig. 5 assert time alarm setting level hysteresis width data input (d) deassert time data output (q) alarm output (sd) fig. 6 fig. 7 aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 2 10 3 10 4 rex1 ( ? ) alarm setting level (mv) veei=open sw=v ee ta=27 ? c peak hold output voltage 0 20mvpp 50mvpp input voltage (vp-p) sw open high sw low
14 CXB1572Q 3. others pay attention to handling this ic because its electrostatic discharge strength is weak. aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa 10 15 20 25 30 35 10 1 10 2 10 3 10 4 10 5 alarm setting level (mv) veei=v ee sw=open ta=27 ? c rex2 ( ? ) aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 3 10 4 10 5 rex3 ( ? ) alarm setting level (mv) veei=open sw=v ee ta=27 ? c fig. 8 fig. 9
15 CXB1572Q example of representative characteristics aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 0.2 0.4 0.6 0.8 1 1.2 bit error rate vs. input amplitude level data input level (mvp-p) bit error rate vee= 3.3v ta=27 c d=155.52mb/s vin=3mvp-p, single input pattern : prbs2 23 1 fig. 10 fig. 11 output rms jitter vs. data input level 70 60 50 40 30 20 10 0 1 10 100 1000 data input level (mvp-p) output rms jitter (ps) vee=3.3v ta=27 c d=155.52mbps vin=3mvp-p, single input pattern : prbs2 23 1 q output waveform 16.4400ns 26.4400ns 36.4400ns ch. 1 = 200.0 mvolts/div timebase = 2.00 ns/div offset = 680.0 mvolts delay = 26.4400 ns vee=3.3v ta=27 c d=155.52mbps vin=3mvp-p, single input pattern : prbs2 23 1
sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package structure package outline unit : mm CXB1572Q 16 sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package structure lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. kokubu ass'y

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